High-Performance DRAMs in Workstation Environments

This paper presents a simulation-based performance study of several of the new high-performance DRAM architectures, each evaluated in a small system organization. These small-system organizations correspond to workstation-class computers and use only a handful of DRAM chips (~10, as opposed to ~1 or ~100). The study covers Fast Page Mode, Extended Data Out, Synchronous, Enhanced Synchronous, Double Data Rate, Synchronous Link, Rambus, and Direct Rambus designs. Our simulations reveal several things: (a) current advanced DRAM technologies are attacking the memory bandwidth problem but not the latency problem; (b) bus transmission speed will soon become a primary factor limiting memory-system performance; (c) the post-L2 address stream still contains significant locality, though it varies from application to application; (d) systems without L2 caches are feasible for lowand medium-speed CPUs (1GHz and below); and (e) as we move to wider buses, row access time becomes more prominent, making it important to investigate techniques to exploit the available locality to decrease access time. Index Terms — DRAM architectures, DRAM performance, DRAM systems, system modeling, DDR DRAM, Direct Rambus DRAM, PC100 SDRAM, DDR2 DRAM. • V. Cuppu and B. Jacob are with the Department of Electrical and Computer Engineering, University of Maryland, College Park, College Park, MD 20742. E-mail: {ramvinod, blj}@eng.umd.edu. • B. Davis is with the Department of Electrical and Computer Engineering, Michigan Technological University, Houghton, MI 49931-1295. E-mail: